//-----------------------------------------------------------------------------
//  Copyright (c) 2013 by HangZhou HenqgQiao Design Corporation. All rights reserved.
//
//  Project  : 
//  Module   : over sample the input data with 8-phases 311M clock
//  Parent   : 
//  Children : 
//
//  Description: 
//
//  Parameters:
//  Local Parameters:
//
//  Notes       : 
//
//  Multicycle and False Paths

module OBSI_DROP(
   input                         OBSI_RESET,

   input                         OBDR_CLK,        // the overhead bytes drop clock
   input                         OBDR_IN_FP,
   input[7:0]                    OBDR_IN_DATA,
   input                         OBDR_IN_DEN,

   input                         OBSI_SYSCLK77,
   input[2:0]                    DSIF_IN_SECTOR_ADDR,
   input[6:0]                    DSIF_IN_BYTE_ADDR,
   output[7:0]                   DSIF_OUT_DATA
   );


wire                             WCTL_FP;
wire                             WCTL_DEN;
wire[7:0]                        WCTL_DATA;
reg[6:0]                         WCTL_BCNT32;
reg[2:0]                         WCTL_SECTOR_CNT8;
wire[2:0]                        WCTL_RSECT_CNT8;

wire                             DTRM_CLKA, DTRM_CLKB;
wire                             DTRM_WEA;
wire[9:0]                        DTRM_ADDRA, DTRM_ADDRB;
wire[7:0]                        DTRM_DINA, DTRM_DOUTB;



wire[2:0]                        GRAY8_IN;
reg[2:0]                         GRAY8_SOURCE;
reg[2:0]                         GRAY8_DESTINATION;
reg[2:0]                         GRAY8_OUT;


   assign WCTL_FP           = OBDR_IN_FP;
   assign WCTL_DEN          = OBDR_IN_DEN;
   assign WCTL_DATA[7:0]    = OBDR_IN_DATA[7:0];

   assign WCTL_RSECT_CNT8[2:0]    = GRAY8_OUT[2:0];
always @( posedge OBSI_RESET or posedge OBDR_CLK ) begin
   if ( OBSI_RESET==1'b1 )
      WCTL_BCNT32[4:0]                              <= 5'd0;
   else begin
      if ( WCTL_FP==1'b1 && WCTL_DEN==1'b1 )
         WCTL_BCNT32[4:0]                           <= 5'd1;
      else if ( WCTL_DEN==1'b1 ) begin
         if ( WCTL_BCNT32[4:0]== 5'd31 )
            WCTL_BCNT32[4:0]                        <= 5'd0;
         else
            WCTL_BCNT32[4:0]                        <= WCTL_BCNT32[4:0] +5'd1;
      end
   end
end

always @( posedge OBSI_RESET or posedge OBDR_CLK ) begin
   if ( OBSI_RESET==1'b1 )
      WCTL_SECTOR_CNT8[2:0]                         <= 3'd0;
   else begin
      if ( WCTL_RSECT_CNT8[2:0]==WCTL_SECTOR_CNT8[2:0] )
         WCTL_SECTOR_CNT8[2:0]                      <= WCTL_SECTOR_CNT8[2:0] +3'd4;
      else if ( WCTL_FP==1'b1 && WCTL_DEN==1'b1 )
         WCTL_SECTOR_CNT8[2:0]                      <= WCTL_SECTOR_CNT8[2:0] +3'd1;
   end
end







// ++++++++++++++++++ DATA RAM read address gray convert   ++++++++++++++++++ //
  assign GRAY8_IN[2:0]         =  DSIF_IN_SECTOR_ADDR[2:0];

always @( posedge OBSI_SYSCLK77 or posedge OBSI_RESET ) begin
   if ( OBSI_RESET==1'b1 )
      GRAY8_SOURCE[2:0]                              <= 3'd0;
   else begin
      case ( GRAY8_IN[2:0] )
      3'b000:  GRAY8_SOURCE[2:0]                     <= 3'b000;
      3'b001:  GRAY8_SOURCE[2:0]                     <= 3'b001;
      3'b010:  GRAY8_SOURCE[2:0]                     <= 3'b011;
      3'b011:  GRAY8_SOURCE[2:0]                     <= 3'b010;
      3'b100:  GRAY8_SOURCE[2:0]                     <= 3'b110;
      3'b101:  GRAY8_SOURCE[2:0]                     <= 3'b111;
      3'b110:  GRAY8_SOURCE[2:0]                     <= 3'b101;
      3'b111:  GRAY8_SOURCE[2:0]                     <= 3'b100;
      default : ;
      endcase
   end
end
always @( posedge OBDR_CLK or posedge OBSI_RESET ) begin
   if ( OBSI_RESET==1'b1 )
      GRAY8_DESTINATION[2:0]                         <= 3'd0;
   else
      GRAY8_DESTINATION[2:0]                         <=GRAY8_SOURCE[2:0];
end
always @( posedge OBDR_CLK or posedge OBSI_RESET ) begin
   if ( OBSI_RESET==1'b1 )
      GRAY8_OUT[2:0]                                 <= 3'd0;
   else begin
      case ( GRAY8_DESTINATION[2:0] )
      3'b000: GRAY8_OUT[2:0]                         <= 3'b000;
      3'b001: GRAY8_OUT[2:0]                         <= 3'b001;
      3'b011: GRAY8_OUT[2:0]                         <= 3'b010;
      3'b010: GRAY8_OUT[2:0]                         <= 3'b011;
      3'b110: GRAY8_OUT[2:0]                         <= 3'b100;
      3'b111: GRAY8_OUT[2:0]                         <= 3'b101;
      3'b101: GRAY8_OUT[2:0]                         <= 3'b110;
      3'b100: GRAY8_OUT[2:0]                         <= 3'b111;
      default : ;
      endcase
   end
end



  assign DTRM_CLKA         = OBDR_CLK;
  assign DTRM_WEA          = WCTL_DEN;
  assign DTRM_ADDRA[9:0]   = { 2'd0, WCTL_SECTOR_CNT8[2:0], WCTL_BCNT32[4:0] };
  assign DTRM_DINA[7:0]    = WCTL_DATA[7:0];

  assign DTRM_CLKB         = OBSI_SYSCLK77;
  assign DTRM_ADDRB[9:0]   = { 2'd0, DSIF_IN_SECTOR_ADDR[2:0], DSIF_IN_BYTE_ADDR[4:0] };
  assign DSIF_OUT_DATA[7:0] = DTRM_DOUTB[7:0];
OBSI_DROP_DTRM                    INST_DTRM(
   .CLKA                          ( DTRM_CLKA ),
   .WEA                           ( DTRM_WEA ),
   .ADDRA                         ( DTRM_ADDRA[9:0] ),
   .DINA                          ( DTRM_DINA[7:0] ),

   .CLKB                          ( DTRM_CLKB ),
   .ADDRB                         ( DTRM_ADDRB[9:0] ),
   .DOUTB                         ( DTRM_DOUTB[7:0] )
   );






endmodule


